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dc.contributor.authorHanna, Amir
dc.contributor.authorHussain, Muhammad Mustafa
dc.date.accessioned2015-03-17T06:08:31Z
dc.date.available2015-03-17T06:08:31Z
dc.date.issued2015-01-07
dc.identifier.citationSi/Ge hetero-structure nanotube tunnel field effect transistor 2015, 117 (1):014310 Journal of Applied Physics
dc.identifier.issn0021-8979
dc.identifier.issn1089-7550
dc.identifier.doi10.1063/1.4905423
dc.identifier.urihttp://hdl.handle.net/10754/346750
dc.description.abstractWe discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.
dc.publisherAIP Publishing
dc.relation.urlhttp://scitation.aip.org/content/aip/journal/jap/117/1/10.1063/1.4905423
dc.rightsArchived with thanks to Journal of Applied Physics
dc.titleSi/Ge hetero-structure nanotube tunnel field effect transistor
dc.typeArticle
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
dc.contributor.departmentElectrical Engineering Program
dc.contributor.departmentIntegrated Nanotechnology Lab
dc.identifier.journalJournal of Applied Physics
dc.eprint.versionPublisher's Version/PDF
dc.contributor.affiliationKing Abdullah University of Science and Technology (KAUST)
kaust.personHanna, Amir
kaust.personHussain, Muhammad Mustafa
refterms.dateFOA2018-06-13T16:16:12Z


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