Fully digital jerk-based chaotic oscillators for high throughput pseudo-random number generators up to 8.77Gbits/s

Abstract

This paper introduces fully digital implementations of four different systems in the 3rd order jerk-equation based chaotic family using the Euler approximation. The digitization approach enables controllable chaotic systems that reliably provide sinusoidal or chaotic output based on a selection input. New systems are introduced, derived using logical and arithmetic operations between two system implementations of different bus widths, with up to 100x higher maximum Lyapunov exponent than the original jerkequation based chaotic systems. The resulting chaotic output is shown to pass the NIST sp. 800-22 statistical test suite for pseudorandom number generators without post-processing by only eliminating the statistically defective bits. The systems are designed in Verilog HDL and experimentally verified on a Xilinx Virtex 4 FPGA for a maximum throughput of 15.59 Gbits/s for the native chaotic output and 8.77 Gbits/s for the resulting pseudo-random number generators