Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors?
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Integrated Nanotechnology Lab
Physical Science and Engineering (PSE) Division
Online Publication Date2012-06-27
Print Publication Date2012-12
Permanent link to this recordhttp://hdl.handle.net/10754/293661
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AbstractDecade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.
CitationFahad HM, Hussain MM (2012) Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors- Sci Rep 2. doi:10.1038/srep00475.
PubMed Central IDPMC3384075
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- Silicon p-FETs from ultrahigh density nanowire arrays.
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- Issue date: 2006 Jun
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- Fabrication of suspended silicon nanowire arrays.
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- Issue date: 2008 May