AuthorsIbrahim, Mohamad A.
AdvisorsKeyes, David E.
Embargo End Date2014-05-11
Permanent link to this recordhttp://hdl.handle.net/10754/293352
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Access RestrictionsAt the time of archiving, the student author of this thesis opted to temporarily restrict access to it. The full text of this thesis became available to the public after the expiration of the embargo on 2014-05-11.
AbstractThis thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.
CitationIbrahim, M. A. (2013). Hardware Realization of Chaos-based Symmetric Video Encryption. KAUST Research Repository. https://doi.org/10.25781/KAUST-2X2DI