Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator
KAUST DepartmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Electrical Engineering Program
Physical Science and Engineering (PSE) Division
Online Publication Date2011-09-28
Print Publication Date2011-08
Permanent link to this recordhttp://hdl.handle.net/10754/236251
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AbstractThis paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.
CitationMansingka AS, Radwan AG, Zidan MA, Salama KN (2011) Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/MWSCAS.2011.6026596.
Conference/Event name54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011