Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator
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Analysis_of_Bus_Width_and_Delay_on_a_Fully_Digital_Signum_Nonlinearity_Chaotic_Oscillator.pdf
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Conference PaperKAUST Department
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) DivisionElectrical Engineering Program
Physical Science and Engineering (PSE) Division
Sensors Lab
Date
2011-09-28Online Publication Date
2011-09-28Print Publication Date
2011-08Permanent link to this record
http://hdl.handle.net/10754/236251
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This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.Citation
Mansingka AS, Radwan AG, Zidan MA, Salama KN (2011) Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/MWSCAS.2011.6026596.Conference/Event name
54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011ae974a485f413a2113503eed53cd6c53
10.1109/MWSCAS.2011.6026596