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dc.contributor.advisorSalama, Khaled Nabil
dc.contributor.authorBarakat, Mohamed L.
dc.date.accessioned2012-07-21T08:22:42Z
dc.date.available2012-07-21T08:22:42Z
dc.date.issued2012-06
dc.identifier.doi10.25781/KAUST-L1NQ3
dc.identifier.urihttp://hdl.handle.net/10754/234953
dc.description.abstractThis thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.
dc.language.isoen
dc.subjectChaos
dc.subjectFPGA
dc.subjectNIST
dc.subjectPost-Processing
dc.subjectBlack and stream ciphers
dc.subjectImage encryption
dc.titleHardware Realization of Chaos Based Symmetric Image Encryption
dc.typeThesis
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
thesis.degree.grantorKing Abdullah University of Science and Technology
dc.contributor.committeememberAl-Naffouri, Tareq Y.
dc.contributor.committeememberAlouini, Mohamed-Slim
thesis.degree.disciplineElectrical Engineering
thesis.degree.nameMaster of Science
refterms.dateFOA2013-06-30T00:00:00Z


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