Highly suppressed interface traps of Al2O3/GaN through interposing a stoichiometric Ga2O3 layer

Al2O3 is a broadly employed dielectric material in GaN high electron mobility transistors. Nevertheless, at the Al2O3/GaN interface, numerous traps induced by nonidealities of the native GaO x layer on the surface of GaN can lead to threshold voltage instability and other reliability issues. In this study, after removing the native GaO x layer, a stoichiometric Ga2O3 layer was sandwiched between Al2O3 and GaN. The interfacial state density of Al2O3/GaN can be reduced by more than two orders of magnitude to an extremely low level of 2.4 × 1010 eV−1 cm−2 at the energy level of 0.36 eV.

I n recent years, GaN high electron mobility transistors (HEMTs) have garnered extensive interest in power and radio-frequency applications owing to their high mobility, high breakdown field, and chemical stability. 1,2) The metal-oxide-semiconductor field-effect transistor is one of the most commonly used structures in GaN HEMTs to suppress the gate leakage current and enlarge the gate voltage swing, the AlGaN/GaN epitaxial wafer typically consists of a thin GaN-cap layer which can further reduce the gate leakage current. 3,4) Among typical gate dielectric materials, such as Al 2 O 3 , 5-7) HfO 2 , 7) and SiO 2 , 8) Al 2 O 3 is one of the most promising candidates because of its high dielectric constant (8)(9)(10), large bandgap (7-9 eV), 9) sufficiently large conduction band offset between GaN and Al 2 O 3 , and mature deposition technology. 5,10) However, due to the poor quality of the native GaO x at the surface of GaN, numerous traps and fixed charges are introduced at the Al 2 O 3 /GaN interface, deteriorating the reliability and shifting the threshold voltage of GaN HEMTs. 11) Previous research on improving the interfacial quality of GaN by controlling the native GaO x layer can be classified into two kinds of strategies. One is to remove the native GaO x through chemical cleaning or in situ inductively coupled plasma cleaning before the gate dielectric deposition. 5,11) For example, Ando et al. used an optimized mixture of chemical solutions to clean the GaN surface, obtaining a low interfacial state density (D it ) value of 3 × 10 10 eV −1 cm −2 at the Al 2 O 3 /GaN interface. 6) Yang et al. removed the native GaO x using NH 3 -Ar plasma cleaning before the atomic layer deposition (ALD) Al 2 O 3 process, achieving a high-performance GaN HEMTs with a small hysteresis of 0.09 V. 11) The other strategy is to introduce a high-quality Ga 2 O 3 layer using thermal oxidation and laser irradiation. 12,13) Nakano et al. achieved a low D it of 5.5 × 10 10 eV −1 cm −2 between Ga 2 O 3 and GaN by oxidizing the GaN in the furnace at 880°C for 5 h. 12) Lee et al. oxidized the n-type GaN sample in a chemical solution under He-Cd laser irradiation, a low interface state density of 2.53 × 10 11 cm −2 eV −1 was obtained. 13) Although Ga 2 O 3 is a suitable gate dielectric material due to the low D it between Ga 2 O 3 and GaN, the gate breakdown electric field is often limited by the smaller bandgap of Ga 2 O 3 (∼4.6 eV) as opposed to other larger bandgap materials, such as Al 2 O 3 (∼8 eV). Therefore, Ga 2 O 3 combined with Al 2 O 3 could be a promising gate dielectric for lower D it , suppressed gate leakage current, and enhanced gate voltage swing simultaneously. In addition, Ga 2 O 3 was deposited by the pulsed laser deposition (PLD) technique in this work, and PLD can offer higher temperature and vacuum in comparison with ALD and sputtering, which will benefit to reduce the interfacial state density and enhance the device performance. 14) In this letter, after removing the native GaO x on GaN, we have grown a thin Ga 2 O 3 interlayer by the PLD technique between Al 2 O 3 and GaN to form the Al 2 O 3 /Ga 2 O 3 /GaN capacitor. The resulting D it was reduced by more than two orders of magnitude to an extremely low level of 2.4 × 10 10 eV −1 cm −2 at the energy level of 0.36 eV compared with the Al 2 O 3 /GaN capacitor.  Fig. 1(b), the thickness of the amorphous Ga 2 O 3 interlayer is around 3 nm.
The GaN samples were cleaned with acetone, isopropyl alcohol, deionized water, and piranha solution successively to remove organic surface contamination. Then, the cleaned samples were immersed in diluted hydrogen fluoride (HF) for 2.5 min to etch away the native GaO x . 15,16) Immediately after the chemical cleaning process, a thin Ga 2 O 3 layer was deposited on a GaN wafer using PLD (Neocera Pioneer 120) with the oxygen pressure of 1 mTorr, laser pulse density of 100 mJ cm −2 , and laser pulse frequency of 1 Hz at 650°C. Subsequently, the sample was transferred to an ALD chamber to deposit a 15 nm Al 2 O 3 layer using the trimethylaluminum (TMA) and O 2 plasma as precursors. One ALD cycle comprises 0.015 s TMA dose under the pressure of 80 mTorr, followed by 3 s N 2 purge, 3 s O 2 plasma treatment with the pressure of 15 mTorr and the power of 300 W and then 3 s N 2 purge under the pressure of 80 mTorr.
For the reference Al 2 O 3 /GaN, after the same solvent cleaning process, 15 nm Al 2 O 3 was deposited on GaN using ALD without removing the native GaO x . The device structure fabrication was accomplished after e-beam evaporation of the Ni/Au (50/100 nm) stack and lift-off procedure. After that, the experimental and reference samples underwent the same post-gate annealing conditions at 500°C under N 2 atmosphere for 5 min. 12) Further increasing annealing temperature can lead to the diffusion of Ni and Au to the underlying substrate. 17) A Keithley 4200A-SCS parameter analyzer was used for all electrical analyses including the capacitancevoltage (C-V ), conductance-voltage (G p /ω-V), and currentvoltage (I-V ) characteristics. As series resistance can cause a serious error in admittance-based measured methods, C-V and G p /ω-V data were corrected in this study. 18) The Ga dangling bonds of the native GaO x at the surface of GaN are often considered responsible for numerous D it between the gate dielectric and GaN. 11,19,20) XPS was used to evaluate the number of the Ga dangling bonds of the native GaO x on the surface of GaN as well as the Ga 2 O 3 grown by PLD technique which were labeled as "GaN" and "Ga 2 O 3 grown by PLD" respectively in Figs. 2(a) and 2(b). The samples were specially prepared for XPS investigations. For the "GaN" sample, it received the solvent pretreatment, XPS was performed immediately after the cleaning process. For the "Ga 2 O 3 grown by PLD" sample, after the solvent and HF cleaning process of the GaN template, a 3 nm thick Ga 2 O 3 layer was deposited on this template, and XPS was also performed immediately. The O 1 s, Ga 3d, and C 1 s corelevel spectra were acquired at a 45°take-off angle, where C 1s peaks at 284.8 eV were used to calibrate the binding energy positions of the Ga 3d and O 1 s XPS signals.
As presented in Fig. 2(a), Ga-N and Ga-O bonds positioned at 19.3 and 20.2 eV are superimposed to fit the Ga 3d signals, consistent with previous publications. 15,21) No obvious peak lower than 18 eV was observed, implying negligible Ga-Ga bonds., 21) the binding energy position of Ga 3d is located at 20.2 eV as shown in Fig. 2(a).
The O 1 s core-level spectra in Fig. 2 The O to Ga atomic ratio is calculated at 0.5:1, which is far from the stoichiometric value of 1.5:1, implying that numerous Ga dangling bonds of the native GaO x layer are on the surface of GaN. Based on the same computational method above, the O to Ga atomic ratio of the Ga 2 O 3 is calculated at 1.4:1, which is close to the stoichiometric 1.5:1 atomic ratio. The  The bidirectional C-V method with the voltage range of −5 to 5 V and the sweeping rate of 0.05 V s −1 was adopted to evaluate the D it of the Al 2 O 3 /GaN and Al 2 O 3 /Ga 2 O 3 /GaN capacitors. For both capacitors, the gate voltage was held at −5 V for 5 min before the measurement to release the trapped electrons. After the capacitance reached the maximum value, the gate voltage was held at 5 V for another 5 min to facilitate the trapping process of electrons under the forward electric field. When the voltage swept back from accumulation to the depletion capacitance region, some trapped electrons did not have enough time to escape from the trapped energy levels. Those trapped electrons could induce an electric field in the capacitor and shift the flat-band voltage to the positive direction in the down sweep C-V measurement. 26) As displayed in Fig. 3(a), the hysteresis can be as large as 0.75 V at the gate voltage of 1.5 V for the capacitor without a Ga 2 O 3 interlayer at 1 MHz, whereas the hysteresis can be reduced to 0.05 V at the same gate voltage for the capacitor with a Ga 2 O 3 interlayer. The small hysteresis in Fig. 3(a) implies the lower D it of Al 2 O 3 /Ga 2 O 3 /GaN compared with the Al 2 O 3 /GaN capacitor.
As displayed in Fig. 3(a), the flat-band voltage of the Al 2 O 3 /Ga 2 O 3 /GaN capacitor is 0.65 V larger than the Al 2 O 3 /GaN capacitor in the up sweep measurement, which is advantageous for the achievement of the enhancementmodel GaN HEMTs. As from the abovementioned discussion, the nonidealities of native GaO x at the surface of GaN can lead to numerous Ga dangling bonds at the interfacial region of Al 2 O 3 /GaN. If the interfacial defects induce energy levels between the conduction minimum of Al 2 O 3 and GaN, the Fermi level cannot move past these energy levels under either positive or negative gate bias. These states can behave like positive fixed charges. 27) Therefore, the positive shift of the flat-band voltage can also be attributed to the interfacial quality ameliorating where the defect-induced positive charges were suppressed after introducing the high-quality Ga 2 O 3 interlayer. In addition, Fig. 3(a) reveals that the accumulation capacitance of the Al 2 O 3 /Ga 2 O 3 /GaN capacitor is smaller than that of its counterpart, resulting from the larger gate dielectric thickness after inserting the Ga 2 O 3 interlayer. Assuming e » 10, the Ga 2 O 3 interlayer thickness is estimated to be 2.88 nm with the C-V measurement which is close the value observed in the TEM image.
As presented in Figs. 3(b) and 3(c), the frequencydependent C-V measurement with a frequency ranging from 1 kHz to 1 MHz was conducted to further analyze the interface trap properties. The voltage dispersion can be as large as 1.3 V when the frequency increases from 1 kHz to 1 MHz with the Al 2 O 3 /GaN capacitor; thus, numerous interfacial traps are present at the Al 2 O 3 /GaN interface. In contrast, in Fig. 3(c), a negligible dispersion exists in the weak accumulation region of the Al 2 O 3 /Ga 2 O 3 /GaN capacitor, and the small frequency dispersion in the strong accumulation region can be attributed to the shunt and series resistance of the capacitor. 28) Therefore, the Ga 2 O 3 interlayer effectively suppressed the frequency dispersion by reducing the Ga dangling bonds induced interfacial traps between Al 2 O 3 and GaN. The conductance method based on the equivalent circuit model was further deployed to quantitatively analyze the interfacial defects of the Al 2 O 3 /GaN and Al 2 O 3 /Ga 2 O 3 /GaN capacitors. 12,29) Six gate voltages were biased around the flat-band voltage in the above C-V curves to probe D it using the conductance method so that the Fermi level can only move within the bandgap of GaN under these gate voltages. 26) For a given gate voltage bias, the frequency of the ac anode signal increased from 1 kHz to 1 MHz gradually, and 28 frequency data points were acquired in one measurement. The G p /ω curve can be acquired from Eq. (2), where ω is the radio frequency of the ac anode signal, C Al O 2 3 is the capacitance in the strong accumulation region of the C-V curves, and G m, and C m are the measured conductance and capacitance, respectively: The parallel conductance as a function of the radio frequency is given by Eq.   Figure 4(c) reveals the D it distribution as a function of the energy levels from the minimum of the conduction band of GaN for the two capacitors with and without a Ga 2 O 3 interlayer. For the Al 2 O 3 /GaN capacitor, the high D it of 9.0 × 10 12 cm −2 eV −1 is detected at the energy level of 0.36 eV. In comparison, a significantly lower D it of 2.4 × 10 10 cm −2 eV −1 is achieved at the same energy levels after introducing the Ga 2 O 3 interlayer. Overall, the D it can be reduced by more than two orders of magnitude in the detected energy levels. As discussed before, compared with the native GaO x , the O to Ga atomic ratio of Ga 2 O 3 is much closer to the stoichiometric value. Therefore, the significantly suppressed D it can be attributed to the reduced Ga dangling bonds after removing the native GaO x and sandwiching the Ga 2 O 3 interlayer. From Fig. 4(c), the densities of deep level traps are higher than those of the shallow level traps in the Al 2 O 3 /Ga 2 O 3 /GaN capacitor. In contrast, the densities of interfacial traps decrease with the increasing energy levels in the Al 2 O 3 /GaN capacitor, implying that different interfacial trap types exist after introducing the Ga 2 O 3 interlayer. In the disorder-induced gap state mode, D it distribution has a Ushaped characteristic, i.e. D it has the minimum value at charge neutrality level E CNL and increases as it moves away from E CNL to the edges of conduction band E C and valence band E V . 30) However, only part of the interface states can be detected with the conductance method as many trapped electrons are in "frozen states" at room temperature which cannot respond to the gate voltage bias. 20,30,31) Therefore, D it shows derivation from the U-shaped distribution which is a commonly observed result. 30,31) In conclusion, a stoichiometric Ga 2 O 3 layer was interposed between Al 2 O 3 and GaN by the PLD technique. Compared with the native GaO x on the surface of GaN, a negligible number of Ga dangling bonds were detected using the XPS measurement with Ga 2 O 3 . Electrical measurement demonstrated that improved interface quality with the