Improved StrongARM latch comparator: Design, analysis and performance evaluation

Handle URI:
http://hdl.handle.net/10754/625683
Title:
Improved StrongARM latch comparator: Design, analysis and performance evaluation
Authors:
Almansouri, Abdullah Saud Mohammed; Al-Turki, Abdullah Turki; Alshehri, Abdullah; Al Attar, Talal; Fariborzi, Hossein ( 0000-0002-7828-0239 )
Abstract:
This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Citation:
Almansouri A, Alturki A, Alshehri A, Al-Attar T, Fariborzi H (2017) Improved StrongARM latch comparator: Design, analysis and performance evaluation. 2017 13th Conference on PhD Research in Microelectronics and Electronics (PRIME). Available: http://dx.doi.org/10.1109/PRIME.2017.7974114.
Publisher:
IEEE
Journal:
2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
Conference/Event name:
13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017
Issue Date:
13-Jul-2017
DOI:
10.1109/PRIME.2017.7974114
Type:
Conference Paper
Additional Links:
http://ieeexplore.ieee.org/document/7974114/
Appears in Collections:
Conference Papers; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorAlmansouri, Abdullah Saud Mohammeden
dc.contributor.authorAl-Turki, Abdullah Turkien
dc.contributor.authorAlshehri, Abdullahen
dc.contributor.authorAl Attar, Talalen
dc.contributor.authorFariborzi, Hosseinen
dc.date.accessioned2017-10-03T12:49:33Z-
dc.date.available2017-10-03T12:49:33Z-
dc.date.issued2017-07-13en
dc.identifier.citationAlmansouri A, Alturki A, Alshehri A, Al-Attar T, Fariborzi H (2017) Improved StrongARM latch comparator: Design, analysis and performance evaluation. 2017 13th Conference on PhD Research in Microelectronics and Electronics (PRIME). Available: http://dx.doi.org/10.1109/PRIME.2017.7974114.en
dc.identifier.doi10.1109/PRIME.2017.7974114en
dc.identifier.urihttp://hdl.handle.net/10754/625683-
dc.description.abstractThis paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.en
dc.publisherIEEEen
dc.relation.urlhttp://ieeexplore.ieee.org/document/7974114/en
dc.subjectCapacitanceen
dc.subjectCapacitorsen
dc.subjectClocksen
dc.subjectDelaysen
dc.subjectLatchesen
dc.subjectLogic gatesen
dc.subjectTransistorsen
dc.titleImproved StrongARM latch comparator: Design, analysis and performance evaluationen
dc.typeConference Paperen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.identifier.journal2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)en
dc.conference.date2017-06-12 to 2017-06-15en
dc.conference.name13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017en
dc.conference.locationGiardini Naxos - Taormina, ITAen
kaust.authorAlmansouri, Abdullah Saud Mohammeden
kaust.authorAl-Turki, Abdullah Turkien
kaust.authorAlshehri, Abdullahen
kaust.authorAl Attar, Talalen
kaust.authorFariborzi, Hosseinen
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