Low-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chips

Handle URI:
http://hdl.handle.net/10754/623864
Title:
Low-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chips
Authors:
Riaz, Kashif; Leung, Siu; Fan, Zhiyong; Lee, Yi-Kuen ( 0000-0002-7473-4344 )
Abstract:
Electric cell lysis (ECL) is a promising technique to be integrated with portable lab-on-a-chip without lysing agent due to its simplicity and fast processing. ECL is usually limited by the requirements of high power/voltage and costly fabrication. In this paper, we present low-cost 3-D nano-spikes-based ECL (NSP-ECL) chips for efficient cell lysis at low power consumption. Highly ordered High-Aspect-Ratio (HAR). NSP arrays with controllable dimensions were fabricated on commercial aluminum foils through scalable and electrochemical anodization and etching. The optimized multiple pulse protocols with minimized undesirable electrochemical reactions (gas and bubble generation), common on micro parallel-plate ECL chips. Due to the scalability of fabrication process, 3-D NSPs were fabricated on small chips as well as on 4-in wafers. Phase diagram was constructed by defining critical electric field to induce cell lysis and for cell lysis saturation Esat to define non-ECL and ECL regions for different pulse parameters. NSP-ECL chips have achieved excellent cell lysis efficiencies ηlysis (ca 100%) at low applied voltages (2 V), 2~3 orders of magnitude lower than that of conventional systems. The energy consumption of NSP-ECL chips was 0.5-2 mJ/mL, 3~9 orders of magnitude lower as compared with the other methods (5J/mL-540kJ/mL). [2016-0305]
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Citation:
Riaz K, Leung S-F, Fan Z, Lee Y-K (2017) Low-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chips. Journal of Microelectromechanical Systems: 1–11. Available: http://dx.doi.org/10.1109/jmems.2017.2695639.
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
Journal of Microelectromechanical Systems
Issue Date:
4-May-2017
DOI:
10.1109/jmems.2017.2695639
Type:
Article
ISSN:
1057-7157; 1941-0158
Sponsors:
Hong Kong Research Grants Council[16237816, 16205314]
Additional Links:
http://ieeexplore.ieee.org/document/7919169/
Appears in Collections:
Articles; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorRiaz, Kashifen
dc.contributor.authorLeung, Siuen
dc.contributor.authorFan, Zhiyongen
dc.contributor.authorLee, Yi-Kuenen
dc.date.accessioned2017-05-31T11:23:10Z-
dc.date.available2017-05-31T11:23:10Z-
dc.date.issued2017-05-04en
dc.identifier.citationRiaz K, Leung S-F, Fan Z, Lee Y-K (2017) Low-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chips. Journal of Microelectromechanical Systems: 1–11. Available: http://dx.doi.org/10.1109/jmems.2017.2695639.en
dc.identifier.issn1057-7157en
dc.identifier.issn1941-0158en
dc.identifier.doi10.1109/jmems.2017.2695639en
dc.identifier.urihttp://hdl.handle.net/10754/623864-
dc.description.abstractElectric cell lysis (ECL) is a promising technique to be integrated with portable lab-on-a-chip without lysing agent due to its simplicity and fast processing. ECL is usually limited by the requirements of high power/voltage and costly fabrication. In this paper, we present low-cost 3-D nano-spikes-based ECL (NSP-ECL) chips for efficient cell lysis at low power consumption. Highly ordered High-Aspect-Ratio (HAR). NSP arrays with controllable dimensions were fabricated on commercial aluminum foils through scalable and electrochemical anodization and etching. The optimized multiple pulse protocols with minimized undesirable electrochemical reactions (gas and bubble generation), common on micro parallel-plate ECL chips. Due to the scalability of fabrication process, 3-D NSPs were fabricated on small chips as well as on 4-in wafers. Phase diagram was constructed by defining critical electric field to induce cell lysis and for cell lysis saturation Esat to define non-ECL and ECL regions for different pulse parameters. NSP-ECL chips have achieved excellent cell lysis efficiencies ηlysis (ca 100%) at low applied voltages (2 V), 2~3 orders of magnitude lower than that of conventional systems. The energy consumption of NSP-ECL chips was 0.5-2 mJ/mL, 3~9 orders of magnitude lower as compared with the other methods (5J/mL-540kJ/mL). [2016-0305]en
dc.description.sponsorshipHong Kong Research Grants Council[16237816, 16205314]en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urlhttp://ieeexplore.ieee.org/document/7919169/en
dc.subjectNano-spikesen
dc.subjectelectric cell lysis chipsen
dc.subjectelectrochemical anodization and etching processesen
dc.subjectelectric field enhancementen
dc.subjectenergy-efficienten
dc.subjectlab on chipen
dc.titleLow-Cost Energy-Efficient 3-D Nano-Spikes-Based Electric Cell Lysis Chipsen
dc.typeArticleen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.identifier.journalJournal of Microelectromechanical Systemsen
dc.contributor.institutionDepartment of Mechanical and Aerospace Engineering, Hong Kong University of Science and Technology, Hong Kongen
dc.contributor.institutionDepartment of Electrical Engineering, Information Technology University, Lahore 54000, Pakistanen
dc.contributor.institutionDepartment of Electronic and Computer Engineering, Hong Kong University of Science and Technology, Hong Kongen
kaust.authorLeung, Siuen
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