A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

Handle URI:
http://hdl.handle.net/10754/622499
Title:
A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers
Authors:
Omran, Hesham; Alhoshany, Abdulaziz; Alahmadi, Hamzah ( 0000-0003-3064-9671 ) ; Salama, Khaled N. ( 0000-0001-7742-1282 )
Abstract:
A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Citation:
Omran H, Alhoshany A, Alahmadi H, Salama KN (2016) A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers: 1–12. Available: http://dx.doi.org/10.1109/TCSI.2016.2608905.
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
IEEE Transactions on Circuits and Systems I: Regular Papers
Issue Date:
16-Nov-2016
DOI:
10.1109/TCSI.2016.2608905
Type:
Article
ISSN:
1549-8328; 1558-0806
Sponsors:
The authors would like to thank the reviewers for their valuable and stimulating comments.
Additional Links:
http://ieeexplore.ieee.org/document/7744463/
Appears in Collections:
Articles; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorOmran, Heshamen
dc.contributor.authorAlhoshany, Abdulazizen
dc.contributor.authorAlahmadi, Hamzahen
dc.contributor.authorSalama, Khaled N.en
dc.date.accessioned2017-01-02T09:55:27Z-
dc.date.available2017-01-02T09:55:27Z-
dc.date.issued2016-11-16en
dc.identifier.citationOmran H, Alhoshany A, Alahmadi H, Salama KN (2016) A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers. IEEE Transactions on Circuits and Systems I: Regular Papers: 1–12. Available: http://dx.doi.org/10.1109/TCSI.2016.2608905.en
dc.identifier.issn1549-8328en
dc.identifier.issn1558-0806en
dc.identifier.doi10.1109/TCSI.2016.2608905en
dc.identifier.urihttp://hdl.handle.net/10754/622499-
dc.description.abstractA 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.en
dc.description.sponsorshipThe authors would like to thank the reviewers for their valuable and stimulating comments.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urlhttp://ieeexplore.ieee.org/document/7744463/en
dc.subjectsuccessive-approximation (SAR)en
dc.subjectCapacitance-to-digital converter (CDC)en
dc.subjectcapacitive sensor interface circuiten
dc.subjectcapacitor arrayen
dc.subjectCMOSen
dc.subjectenergyefficienten
dc.subjectlow-poweren
dc.subjectMEMS pressure sensor readout circuiten
dc.titleA 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiersen
dc.typeArticleen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.identifier.journalIEEE Transactions on Circuits and Systems I: Regular Papersen
dc.contributor.institutionIntegrated Circuits Lab, Faculty of Engineering, Ain Shams University, Cairo 11566, Egypt.en
kaust.authorAlhoshany, Abdulazizen
kaust.authorAlahmadi, Hamzahen
kaust.authorSalama, Khaled N.en
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