Handle URI:
http://hdl.handle.net/10754/598227
Title:
Logical inference techniques for loop parallelization
Authors:
Oancea, Cosmin E.; Rauchwerger, Lawrence
Abstract:
This paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = Ø, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) ⇒ S = Ø). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F(S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECTCLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers. Copyright © 2012 ACM.
Citation:
Oancea CE, Rauchwerger L (2012) Logical inference techniques for loop parallelization. Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation - PLDI ’12. Available: http://dx.doi.org/10.1145/2254064.2254124.
Publisher:
Association for Computing Machinery (ACM)
Journal:
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation - PLDI '12
KAUST Grant Number:
KUS-C1-016-04
Issue Date:
2012
DOI:
10.1145/2254064.2254124
Type:
Conference Paper
Sponsors:
This work was supported in part by NSF awards CRI-0551685,CCF-0833199, CCF-0830753, IIS-0917266, NSF/DNDO award2008-DN-077-ARI018-02, by the DOE NNSA PSAAP grant DEFC52-08NA28616, IBM, Intel, Oracle/Sun and Award KUS-C1-016-04, made by King Abdullah University of Science and Technology(KAUST). Since November 2011 Cosmin Oancea was supportedby Danish Strategic Research Council, for the HIPERFITresearch center under contract 10-092299.
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Full metadata record

DC FieldValue Language
dc.contributor.authorOancea, Cosmin E.en
dc.contributor.authorRauchwerger, Lawrenceen
dc.date.accessioned2016-02-25T13:39:59Zen
dc.date.available2016-02-25T13:39:59Zen
dc.date.issued2012en
dc.identifier.citationOancea CE, Rauchwerger L (2012) Logical inference techniques for loop parallelization. Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation - PLDI ’12. Available: http://dx.doi.org/10.1145/2254064.2254124.en
dc.identifier.doi10.1145/2254064.2254124en
dc.identifier.urihttp://hdl.handle.net/10754/598227en
dc.description.abstractThis paper presents a fully automatic approach to loop parallelization that integrates the use of static and run-time analysis and thus overcomes many known difficulties such as nonlinear and indirect array indexing and complex control flow. Our hybrid analysis framework validates the parallelization transformation by verifying the independence of the loop's memory references. To this end it represents array references using the USR (uniform set representation) language and expresses the independence condition as an equation, S = Ø, where S is a set expression representing array indexes. Using a language instead of an array-abstraction representation for S results in a smaller number of conservative approximations but exhibits a potentially-high runtime cost. To alleviate this cost we introduce a language translation F from the USR set-expression language to an equally rich language of predicates (F(S) ⇒ S = Ø). Loop parallelization is then validated using a novel logic inference algorithm that factorizes the obtained complex predicates (F(S)) into a sequence of sufficient-independence conditions that are evaluated first statically and, when needed, dynamically, in increasing order of their estimated complexities. We evaluate our automated solution on 26 benchmarks from PERFECTCLUB and SPEC suites and show that our approach is effective in parallelizing large, complex loops and obtains much better full program speedups than the Intel and IBM Fortran compilers. Copyright © 2012 ACM.en
dc.description.sponsorshipThis work was supported in part by NSF awards CRI-0551685,CCF-0833199, CCF-0830753, IIS-0917266, NSF/DNDO award2008-DN-077-ARI018-02, by the DOE NNSA PSAAP grant DEFC52-08NA28616, IBM, Intel, Oracle/Sun and Award KUS-C1-016-04, made by King Abdullah University of Science and Technology(KAUST). Since November 2011 Cosmin Oancea was supportedby Danish Strategic Research Council, for the HIPERFITresearch center under contract 10-092299.en
dc.publisherAssociation for Computing Machinery (ACM)en
dc.subjectAuto-parallelizationen
dc.subjectIndependence predicatesen
dc.subjectUSRen
dc.titleLogical inference techniques for loop parallelizationen
dc.typeConference Paperen
dc.identifier.journalProceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation - PLDI '12en
dc.contributor.institutionKobenhavns Universitet, Copenhagen, Denmarken
dc.contributor.institutionTexas A and M University, College Station, United Statesen
kaust.grant.numberKUS-C1-016-04en
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