Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

Handle URI:
http://hdl.handle.net/10754/594194
Title:
Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration
Authors:
Pirro, Luca ( 0000-0002-4197-5491 ) ; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin
Abstract:
Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Electrical Engineering Program; Integrated Nanotechnology Lab
Citation:
Pirro L, Diab A, Ionica I, Ghibaudo G, Faraone L, et al. (2015) Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration. IEEE Transactions on Electron Devices 62: 2717–2723. Available: http://dx.doi.org/10.1109/ted.2015.2454438.
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
IEEE Transactions on Electron Devices
Issue Date:
Sep-2015
DOI:
10.1109/ted.2015.2454438
Type:
Article
ISSN:
0018-9383; 1557-9646
Sponsors:
Soitec, Bernin, France; European ENIAC Projects Places2be
Appears in Collections:
Articles; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorPirro, Lucaen
dc.contributor.authorDiab, Amer El Hajjen
dc.contributor.authorIonica, Irinaen
dc.contributor.authorGhibaudo, Gerarden
dc.contributor.authorFaraone, Lorenzoen
dc.contributor.authorCristoloveanu, Sorinen
dc.date.accessioned2016-01-19T13:23:34Zen
dc.date.available2016-01-19T13:23:34Zen
dc.date.issued2015-09en
dc.identifier.citationPirro L, Diab A, Ionica I, Ghibaudo G, Faraone L, et al. (2015) Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration. IEEE Transactions on Electron Devices 62: 2717–2723. Available: http://dx.doi.org/10.1109/ted.2015.2454438.en
dc.identifier.issn0018-9383en
dc.identifier.issn1557-9646en
dc.identifier.doi10.1109/ted.2015.2454438en
dc.identifier.urihttp://hdl.handle.net/10754/594194en
dc.description.abstractRecent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.en
dc.description.sponsorshipSoitec, Bernin, Franceen
dc.description.sponsorshipEuropean ENIAC Projects Places2been
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectFrequency dependenceen
dc.subjectmobilityen
dc.subjectpseudo-MOSFET (Ψ-MOSFET)en
dc.subjectRC modelen
dc.subjectsilicon on insulator (SOI)en
dc.subjectsplit C-V.en
dc.titleSplit-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configurationen
dc.typeArticleen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.identifier.journalIEEE Transactions on Electron Devicesen
dc.contributor.institutionUniv. Grenoble Alpes, IMEP-LAHC, Minatec, Grenoble-ING, Grenoble, Franceen
dc.contributor.institutionCNRS, IMEP-LAHC, Grenoble, Franceen
dc.contributor.institutionMicroelectronics Research Group, School of Electrical, Electronic and Computer Engineering, University of Western Australia, Crawley, WA, Australiaen
kaust.authorDiab, Amer El Hajjen
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