Cleaning Challenges of High-κ/Metal Gate Structures

Handle URI:
http://hdl.handle.net/10754/575837
Title:
Cleaning Challenges of High-κ/Metal Gate Structures
Authors:
Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 ) ; Shamiryan, Denis G.; Paraschiv, Vasile; Sano, Kenichi; Reinhardt, Karen A.
Abstract:
High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.
KAUST Department:
Electrical Engineering Program
Publisher:
Wiley-Blackwell
Journal:
Handbook of Cleaning in Semiconductor Manufacturing
Issue Date:
20-Dec-2010
DOI:
10.1002/9781118071748.ch7
Type:
Book Chapter
ISBN:
9780470625958
Appears in Collections:
Electrical Engineering Program; Book Chapters

Full metadata record

DC FieldValue Language
dc.contributor.authorHussain, Muhammad Mustafaen
dc.contributor.authorShamiryan, Denis G.en
dc.contributor.authorParaschiv, Vasileen
dc.contributor.authorSano, Kenichien
dc.contributor.authorReinhardt, Karen A.en
dc.date.accessioned2015-08-24T09:54:55Zen
dc.date.available2015-08-24T09:54:55Zen
dc.date.issued2010-12-20en
dc.identifier.isbn9780470625958en
dc.identifier.doi10.1002/9781118071748.ch7en
dc.identifier.urihttp://hdl.handle.net/10754/575837en
dc.description.abstractHigh-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.en
dc.publisherWiley-Blackwellen
dc.subjectChemical oxideen
dc.subjectDual metal gateen
dc.subjectGalvanic corrosionen
dc.subjectGate-firsten
dc.subjectGate-lasten
dc.subjectHigh-κ gate dielectricsen
dc.subjectHigh-κ removalen
dc.subjectHigh-κ/metal gateen
dc.subjectInterfacial oxideen
dc.subjectMetal gate electrodeen
dc.titleCleaning Challenges of High-κ/Metal Gate Structuresen
dc.typeBook Chapteren
dc.contributor.departmentElectrical Engineering Programen
dc.identifier.journalHandbook of Cleaning in Semiconductor Manufacturingen
dc.contributor.institutionIMEC, Leuven, Belgiumen
dc.contributor.institutionSilicon Light Machines, San Jose, CA, United Statesen
dc.contributor.institutionCameo Consulting, San Jose, CA, United Statesen
kaust.authorHussain, Muhammad Mustafaen
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