Fibonacci-based hardware post-processing for non-autonomous signum hyperchaotic system

Handle URI:
http://hdl.handle.net/10754/564830
Title:
Fibonacci-based hardware post-processing for non-autonomous signum hyperchaotic system
Authors:
Mansingka, Abhinav S.; Barakat, Mohamed L.; Zidan, Mohammed A. ( 0000-0003-3843-814X ) ; Radwan, Ahmed Gomaa; Salama, Khaled N. ( 0000-0001-7742-1282 )
Abstract:
This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB-PRNGs. © 2013 IEEE.
KAUST Department:
Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Sensors Lab
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2013 International Conference on IT Convergence and Security (ICITCS)
Conference/Event name:
2013 3rd International Conference on IT Convergence and Security, ICITCS 2013
Issue Date:
Dec-2013
DOI:
10.1109/ICITCS.2013.6717834
Type:
Conference Paper
ISBN:
9781479928453
Appears in Collections:
Conference Papers; Electrical Engineering Program; Sensors Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorMansingka, Abhinav S.en
dc.contributor.authorBarakat, Mohamed L.en
dc.contributor.authorZidan, Mohammed A.en
dc.contributor.authorRadwan, Ahmed Gomaaen
dc.contributor.authorSalama, Khaled N.en
dc.date.accessioned2015-08-04T07:17:37Zen
dc.date.available2015-08-04T07:17:37Zen
dc.date.issued2013-12en
dc.identifier.isbn9781479928453en
dc.identifier.doi10.1109/ICITCS.2013.6717834en
dc.identifier.urihttp://hdl.handle.net/10754/564830en
dc.description.abstractThis paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB-PRNGs. © 2013 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subjectFibonaccien
dc.subjectFPGAen
dc.subjectHyperchaosen
dc.subjectPost-processingen
dc.titleFibonacci-based hardware post-processing for non-autonomous signum hyperchaotic systemen
dc.typeConference Paperen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentSensors Laben
dc.identifier.journal2013 International Conference on IT Convergence and Security (ICITCS)en
dc.conference.date16 December 2013 through 18 December 2013en
dc.conference.name2013 3rd International Conference on IT Convergence and Security, ICITCS 2013en
dc.conference.locationMacauen
dc.contributor.institutionApplied Engineering Mathematics, Cairo University, Egypten
dc.contributor.institutionNISC Research Center, Nile University, Cairo, Egypten
kaust.authorMansingka, Abhinav S.en
kaust.authorBarakat, Mohamed L.en
kaust.authorZidan, Mohammed A.en
kaust.authorSalama, Khaled N.en
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