Tin (Sn) for enhancing performance in silicon CMOS

Handle URI:
http://hdl.handle.net/10754/564809
Title:
Tin (Sn) for enhancing performance in silicon CMOS
Authors:
Hussain, Aftab M. ( 0000-0002-9516-9428 ) ; Fahad, Hossain M.; Singh, Nirpendra ( 0000-0001-8043-0403 ) ; Sevilla, Galo T. ( 0000-0002-9419-4437 ) ; Schwingenschlögl, Udo ( 0000-0003-4179-7231 ) ; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 )
Abstract:
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.
KAUST Department:
Electrical Engineering Program; Integrated Nanotechnology Lab; Materials Science and Engineering Program; Physical Sciences and Engineering (PSE) Division; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Computational Physics and Materials Science (CPMS)
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)
Conference/Event name:
2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013
Issue Date:
Oct-2013
DOI:
10.1109/NMDC.2013.6707470
Type:
Conference Paper
ISBN:
9781479933877
Appears in Collections:
Conference Papers; Physical Sciences and Engineering (PSE) Division; Electrical Engineering Program; Materials Science and Engineering Program; Integrated Nanotechnology Lab; Computational Physics and Materials Science (CPMS); Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorHussain, Aftab M.en
dc.contributor.authorFahad, Hossain M.en
dc.contributor.authorSingh, Nirpendraen
dc.contributor.authorSevilla, Galo T.en
dc.contributor.authorSchwingenschlögl, Udoen
dc.contributor.authorHussain, Muhammad Mustafaen
dc.date.accessioned2015-08-04T07:16:45Zen
dc.date.available2015-08-04T07:16:45Zen
dc.date.issued2013-10en
dc.identifier.isbn9781479933877en
dc.identifier.doi10.1109/NMDC.2013.6707470en
dc.identifier.urihttp://hdl.handle.net/10754/564809en
dc.description.abstractWe study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon. © 2013 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleTin (Sn) for enhancing performance in silicon CMOSen
dc.typeConference Paperen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.contributor.departmentMaterials Science and Engineering Programen
dc.contributor.departmentPhysical Sciences and Engineering (PSE) Divisionen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentComputational Physics and Materials Science (CPMS)en
dc.identifier.journal2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)en
dc.conference.date6 October 2013 through 9 October 2013en
dc.conference.name2013 IEEE 8th Nanotechnology Materials and Devices Conference, IEEE NMDC 2013en
dc.conference.locationTainanen
kaust.authorHussain, Aftab M.en
kaust.authorFahad, Hossain M.en
kaust.authorSingh, Nirpendraen
kaust.authorSevilla, Galo T.en
kaust.authorSchwingenschlögl, Udoen
kaust.authorHussain, Muhammad Mustafaen
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