Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing

Handle URI:
http://hdl.handle.net/10754/564587
Title:
Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing
Authors:
Rojas, Jhonathan Prieto ( 0000-0001-7848-1121 ) ; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 )
Abstract:
We present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si 3N4) based spacer formation via reactive ion etching. Control of Si3N4 thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control. © 2012 IEEE.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Electrical Engineering Program; Integrated Nanotechnology Lab
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO)
Conference/Event name:
2012 12th IEEE International Conference on Nanotechnology, NANO 2012
Issue Date:
Aug-2012
DOI:
10.1109/NANO.2012.6322056
Type:
Conference Paper
ISSN:
19449399
ISBN:
9781467321983
Appears in Collections:
Conference Papers; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorRojas, Jhonathan Prietoen
dc.contributor.authorHussain, Muhammad Mustafaen
dc.date.accessioned2015-08-04T07:04:35Zen
dc.date.available2015-08-04T07:04:35Zen
dc.date.issued2012-08en
dc.identifier.isbn9781467321983en
dc.identifier.issn19449399en
dc.identifier.doi10.1109/NANO.2012.6322056en
dc.identifier.urihttp://hdl.handle.net/10754/564587en
dc.description.abstractWe present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si 3N4) based spacer formation via reactive ion etching. Control of Si3N4 thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control. © 2012 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleSub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturingen
dc.typeConference Paperen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.identifier.journal2012 12th IEEE International Conference on Nanotechnology (IEEE-NANO)en
dc.conference.date20 August 2012 through 23 August 2012en
dc.conference.name2012 12th IEEE International Conference on Nanotechnology, NANO 2012en
dc.conference.locationBirminghamen
dc.contributor.institutionIntegrated Nanotechnology Lab, Electrical Engineering Program, Saudi Arabiaen
kaust.authorRojas, Jhonathan Prietoen
kaust.authorHussain, Muhammad Mustafaen
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