Design, implementation and analysis of fully digital 1-D controllable multiscroll chaos

Handle URI:
http://hdl.handle.net/10754/564471
Title:
Design, implementation and analysis of fully digital 1-D controllable multiscroll chaos
Authors:
Mansingka, Abhinav S.; Radwan, Ahmed G.; Salama, Khaled N. ( 0000-0001-7742-1282 )
Abstract:
This paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion. © 2011 IEEE.
KAUST Department:
Electrical Engineering Program; Physical Sciences and Engineering (PSE) Division; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Sensors Lab
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
ICM 2011 Proceeding
Conference/Event name:
2011 23rd International Conference on Microelectronics, ICM 2011
Issue Date:
Dec-2011
DOI:
10.1109/ICM.2011.6177371
Type:
Conference Paper
ISBN:
9781457722073
Appears in Collections:
Conference Papers; Physical Sciences and Engineering (PSE) Division; Electrical Engineering Program; Sensors Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorMansingka, Abhinav S.en
dc.contributor.authorRadwan, Ahmed G.en
dc.contributor.authorSalama, Khaled N.en
dc.date.accessioned2015-08-04T07:01:51Zen
dc.date.available2015-08-04T07:01:51Zen
dc.date.issued2011-12en
dc.identifier.isbn9781457722073en
dc.identifier.doi10.1109/ICM.2011.6177371en
dc.identifier.urihttp://hdl.handle.net/10754/564471en
dc.description.abstractThis paper introduces the fully digital implementation of a 1-D multiscroll chaos generator based on a staircase nonlinearity in the 3rd-order jerk system using the Euler approximation. For the first time, digital design is exploited to provide real-time controllability of (i) number of scrolls, (ii) position in 1-D space, (iii) Euler step size and (iv) system parameter. The effect of variations in these fields on the maximum Lyapunov exponent (MLE) is analyzed. The system is implemented using Verilog HDL and synthesized on an Xilinx Virtex 4 FPGA, exhibiting area utilization less than 3.5% and high performance with experimentally verified throughput up to 3.33 Gbits/s. This fully digital system enables applications in modulation schemes and chaos-based cryptosystems without analog to digital conversion. © 2011 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleDesign, implementation and analysis of fully digital 1-D controllable multiscroll chaosen
dc.typeConference Paperen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentPhysical Sciences and Engineering (PSE) Divisionen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentSensors Laben
dc.identifier.journalICM 2011 Proceedingen
dc.conference.date19 December 2011 through 22 December 2011en
dc.conference.name2011 23rd International Conference on Microelectronics, ICM 2011en
dc.conference.locationHammameten
dc.contributor.institutionDepartment of Engineering Mathematics, Faculty of Engineering, Cairo University, Cairo, Egypten
kaust.authorMansingka, Abhinav S.en
kaust.authorRadwan, Ahmed G.en
kaust.authorSalama, Khaled N.en
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