A low-power digital frequency divider for system-on-a-chip applications

Handle URI:
http://hdl.handle.net/10754/564406
Title:
A low-power digital frequency divider for system-on-a-chip applications
Authors:
Omran, Hesham ( 0000-0002-0117-7364 ) ; Sharaf, Khaled M W; Ibrahim, Magdi Marzouk
Abstract:
In this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.
KAUST Department:
Electrical Engineering Program
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
Conference/Event name:
54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Issue Date:
Aug-2011
DOI:
10.1109/MWSCAS.2011.6026674
Type:
Conference Paper
ISSN:
15483746
ISBN:
9781612848570
Appears in Collections:
Conference Papers; Electrical Engineering Program

Full metadata record

DC FieldValue Language
dc.contributor.authorOmran, Heshamen
dc.contributor.authorSharaf, Khaled M Wen
dc.contributor.authorIbrahim, Magdi Marzouken
dc.date.accessioned2015-08-04T06:26:32Zen
dc.date.available2015-08-04T06:26:32Zen
dc.date.issued2011-08en
dc.identifier.isbn9781612848570en
dc.identifier.issn15483746en
dc.identifier.doi10.1109/MWSCAS.2011.6026674en
dc.identifier.urihttp://hdl.handle.net/10754/564406en
dc.description.abstractIn this paper, an idea for a new frequency divider architecture is proposed. The divider is based on a coarse-fine architecture. The coarse block operates at a low frequency to save power consumption and it selectively enables the fine block which operates at the high input frequency. The proposed divider has the advantages of synchronous divider, but with lower power consumption and higher operation speed. The design can achieve a wide division range with a minor effect on power consumption and speed. The architecture was implemented on a complex programmable logic device (CPLD) to verify its operation. Experimental measurements validate system operation with power reduction greater than 40%. © 2011 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleA low-power digital frequency divider for system-on-a-chip applicationsen
dc.typeConference Paperen
dc.contributor.departmentElectrical Engineering Programen
dc.identifier.journal2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)en
dc.conference.date7 August 2011 through 10 August 2011en
dc.conference.name54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011en
dc.conference.locationSeoulen
dc.contributor.institutionElectronics and Communications Engineering Department, Faculty of Engineering, Ain Shams University, Cairo, Egypten
kaust.authorOmran, Heshamen
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