Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

Handle URI:
http://hdl.handle.net/10754/564284
Title:
Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt
Authors:
Hinkle, Christopher L.; Galatage, Rohit V.; Chapman, Richard A.; Vogel, Eric M.; Alshareef, Husam N. ( 0000-0001-5029-2142 ) ; Freeman, Clive M.; Wimmer, Erich; Niimi, Hiroaki; Li-Fatou, Andrei V.; Shaw, Judy B.; Chambers, James J.
Abstract:
In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.
KAUST Department:
Physical Sciences and Engineering (PSE) Division; Materials Science and Engineering Program; Functional Nanomaterials and Devices Research Group
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2010 Symposium on VLSI Technology
Conference/Event name:
2010 Symposium on VLSI Technology, VLSIT 2010
Issue Date:
Jun-2010
DOI:
10.1109/VLSIT.2010.5556220
Type:
Conference Paper
ISSN:
07431562
ISBN:
9781424476374
Appears in Collections:
Conference Papers; Physical Sciences and Engineering (PSE) Division; Materials Science and Engineering Program

Full metadata record

DC FieldValue Language
dc.contributor.authorHinkle, Christopher L.en
dc.contributor.authorGalatage, Rohit V.en
dc.contributor.authorChapman, Richard A.en
dc.contributor.authorVogel, Eric M.en
dc.contributor.authorAlshareef, Husam N.en
dc.contributor.authorFreeman, Clive M.en
dc.contributor.authorWimmer, Erichen
dc.contributor.authorNiimi, Hiroakien
dc.contributor.authorLi-Fatou, Andrei V.en
dc.contributor.authorShaw, Judy B.en
dc.contributor.authorChambers, James J.en
dc.date.accessioned2015-08-04T06:22:08Zen
dc.date.available2015-08-04T06:22:08Zen
dc.date.issued2010-06en
dc.identifier.isbn9781424476374en
dc.identifier.issn07431562en
dc.identifier.doi10.1109/VLSIT.2010.5556220en
dc.identifier.urihttp://hdl.handle.net/10754/564284en
dc.description.abstractIn this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.titleDipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vten
dc.typeConference Paperen
dc.contributor.departmentPhysical Sciences and Engineering (PSE) Divisionen
dc.contributor.departmentMaterials Science and Engineering Programen
dc.contributor.departmentFunctional Nanomaterials and Devices Research Groupen
dc.identifier.journal2010 Symposium on VLSI Technologyen
dc.conference.date15 June 2010 through 17 June 2010en
dc.conference.name2010 Symposium on VLSI Technology, VLSIT 2010en
dc.conference.locationHonolulu, HIen
dc.contributor.institutionDepartment of Materials Science and Engineering, University of Texas at Dallas, Richardson, TX 75080, United Statesen
dc.contributor.institutionMaterials Design, Incorporated, Angel Fire, NM, 87710, United Statesen
dc.contributor.institutionAdvanced CMOS, Texas Instruments, Incorporated, Dallas, TX 75243, United Statesen
kaust.authorAlshareef, Husam N.en
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