Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS

Handle URI:
http://hdl.handle.net/10754/564259
Title:
Design and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMS
Authors:
Dadgour, Hamed F.; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 ) ; Smith, Casey Eben; Banerjee, Kaustav
Abstract:
Nano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated double-electrode NEMS" structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoulli's beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models "underestimate" the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors. © Copyright 2010 ACM.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Electrical Engineering Program; Integrated Nanotechnology Lab
Publisher:
Association for Computing Machinery (ACM)
Journal:
Proceedings of the 47th Design Automation Conference on - DAC '10
Conference/Event name:
47th Design Automation Conference, DAC '10
Issue Date:
2010
DOI:
10.1145/1837274.1837498
Type:
Conference Paper
ISSN:
0738100X
ISBN:
9781450300025
Appears in Collections:
Conference Papers; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorDadgour, Hamed F.en
dc.contributor.authorHussain, Muhammad Mustafaen
dc.contributor.authorSmith, Casey Ebenen
dc.contributor.authorBanerjee, Kaustaven
dc.date.accessioned2015-08-04T06:21:02Zen
dc.date.available2015-08-04T06:21:02Zen
dc.date.issued2010en
dc.identifier.isbn9781450300025en
dc.identifier.issn0738100Xen
dc.identifier.doi10.1145/1837274.1837498en
dc.identifier.urihttp://hdl.handle.net/10754/564259en
dc.description.abstractNano-Electro-Mechanical Switches (NEMS) are among the most promising emerging devices due to their near-zero subthreshold-leakage currents. This paper reports device fabrication and modeling, as well as novel logic gate design using "laterally-actuated double-electrode NEMS" structures. The new device structure has several advantages over existing NEMS architectures such as being immune to impact bouncing and release vibrations (unlike a vertically-actuated NEMS) and offer higher flexibility to implement compact logic gates (unlike a single-electrode NEMS). A comprehensive analytical framework is developed to model different properties of these devices by solving the Euler-Bernoulli's beam equation. The proposed model is validated using measurement data for the fabricated devices. It is shown that by ignoring the non-uniformity of the electrostatic force distribution, the existing models "underestimate" the actual value of Vpull-in and Vpull-out. Furthermore, novel energy efficient NEMS-based circuit topologies are introduced to implement compact inverter, NAND, NOR and XOR gates. For instance, the proposed XOR gate can be implemented by using only two NEMS devices compared to that of a static CMOS-based XOR gate that requires at least 10 transistors. © Copyright 2010 ACM.en
dc.publisherAssociation for Computing Machinery (ACM)en
dc.subjectEnergy-efficient electronicsen
dc.subjectLaterally-actuated NEMSen
dc.subjectLogic designen
dc.subjectNano-electro-mechanical switchesen
dc.subjectProcess variationen
dc.subjectSteep-subthreshold switchen
dc.titleDesign and analysis of compact ultra energy-efficient logic gates using laterally-actuated double-electrode NEMSen
dc.typeConference Paperen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.identifier.journalProceedings of the 47th Design Automation Conference on - DAC '10en
dc.conference.date13 June 2010 through 18 June 2010en
dc.conference.name47th Design Automation Conference, DAC '10en
dc.conference.locationAnaheim, CAen
dc.contributor.institutionDepartment of Electrical and Computer Engineering, University of California, Santa Barbara, United Statesen
dc.contributor.institutionSEMATECH, Austin, TX, United Statesen
kaust.authorHussain, Muhammad Mustafaen
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