Simulation study of a 3-D device integrating FinFET and UTBFET

Handle URI:
http://hdl.handle.net/10754/563989
Title:
Simulation study of a 3-D device integrating FinFET and UTBFET
Authors:
Fahad, Hossain M.; Hu, Chenming; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 )
Abstract:
By integrating 3-D nonplanar fins and 2-D ultrathin bodies, wavy FinFETs merge two formerly competing technologies on a silicon-on-insulator platform to deliver enhanced transistor performance compared with conventional trigate FinFETs with unprecedented levels of chip-area efficiency. This makes it suitable for ultralarge-scale integration high-performance logic at and beyond the 10-nm technology node.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Integrated Nanotechnology Lab; Electrical Engineering Program
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
IEEE Transactions on Electron Devices
Issue Date:
Jan-2015
DOI:
10.1109/TED.2014.2372695
Type:
Article
ISSN:
00189383
Sponsors:
This work was supported by the Office of Competitive Research Funds through the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, under Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor D. Esseni.
Appears in Collections:
Articles; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorFahad, Hossain M.en
dc.contributor.authorHu, Chenmingen
dc.contributor.authorHussain, Muhammad Mustafaen
dc.date.accessioned2015-08-03T12:22:06Zen
dc.date.available2015-08-03T12:22:06Zen
dc.date.issued2015-01en
dc.identifier.issn00189383en
dc.identifier.doi10.1109/TED.2014.2372695en
dc.identifier.urihttp://hdl.handle.net/10754/563989en
dc.description.abstractBy integrating 3-D nonplanar fins and 2-D ultrathin bodies, wavy FinFETs merge two formerly competing technologies on a silicon-on-insulator platform to deliver enhanced transistor performance compared with conventional trigate FinFETs with unprecedented levels of chip-area efficiency. This makes it suitable for ultralarge-scale integration high-performance logic at and beyond the 10-nm technology node.en
dc.description.sponsorshipThis work was supported by the Office of Competitive Research Funds through the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, under Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor D. Esseni.en
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.subject2-D ultrathin bodies (UTBs)en
dc.subjectFinFETen
dc.subjectultralarge-scale integrationen
dc.subjectwavyen
dc.titleSimulation study of a 3-D device integrating FinFET and UTBFETen
dc.typeArticleen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.contributor.departmentElectrical Engineering Programen
dc.identifier.journalIEEE Transactions on Electron Devicesen
dc.contributor.institutionGraduate School, University of California at BerkeleyBerkeley, CA, United Statesen
kaust.authorFahad, Hossain M.en
kaust.authorHussain, Muhammad Mustafaen
All Items in KAUST are protected by copyright, with all rights reserved, unless otherwise indicated.