Hardware stream cipher with controllable chaos generator for colour image encryption

Handle URI:
http://hdl.handle.net/10754/563320
Title:
Hardware stream cipher with controllable chaos generator for colour image encryption
Authors:
Barakat, Mohamed L.; Mansingka, Abhinav S.; Radwan, Ahmed Gomaa; Salama, Khaled N. ( 0000-0001-7742-1282 )
Abstract:
This study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.
KAUST Department:
Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Sensors Lab
Publisher:
Institution of Engineering and Technology (IET)
Journal:
IET Image Processing
Issue Date:
1-Jan-2014
DOI:
10.1049/iet-ipr.2012.0586
Type:
Article
ISSN:
17519659
Appears in Collections:
Articles; Electrical Engineering Program; Sensors Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorBarakat, Mohamed L.en
dc.contributor.authorMansingka, Abhinav S.en
dc.contributor.authorRadwan, Ahmed Gomaaen
dc.contributor.authorSalama, Khaled N.en
dc.date.accessioned2015-08-03T11:45:39Zen
dc.date.available2015-08-03T11:45:39Zen
dc.date.issued2014-01-01en
dc.identifier.issn17519659en
dc.identifier.doi10.1049/iet-ipr.2012.0586en
dc.identifier.urihttp://hdl.handle.net/10754/563320en
dc.description.abstractThis study presents hardware realisation of chaos-based stream cipher utilised for image encryption applications. A third-order chaotic system with signum non-linearity is implemented and a new post processing technique is proposed to eliminate the bias from the original chaotic sequence. The proposed stream cipher utilises the processed chaotic output to mask and diffuse input pixels through several stages of XORing and bit permutations. The performance of the cipher is tested with several input images and compared with previously reported systems showing superior security and higher hardware efficiency. The system is experimentally verified on XilinxVirtex 4 field programmable gate array (FPGA) achieving small area utilisation and a throughput of 3.62 Gb/s. © The Institution of Engineering and Technology 2013.en
dc.publisherInstitution of Engineering and Technology (IET)en
dc.titleHardware stream cipher with controllable chaos generator for colour image encryptionen
dc.typeArticleen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentSensors Laben
dc.identifier.journalIET Image Processingen
dc.contributor.institutionDepartment of Engineering Mathematics, Faculty of Engineering, Cairo University, Giza, Egypten
kaust.authorBarakat, Mohamed L.en
kaust.authorMansingka, Abhinav S.en
kaust.authorSalama, Khaled N.en
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