Generalized hardware post-processing technique for chaos-based pseudorandom number generators

Handle URI:
http://hdl.handle.net/10754/562799
Title:
Generalized hardware post-processing technique for chaos-based pseudorandom number generators
Authors:
Barakat, Mohamed L.; Mansingka, Abhinav S.; Radwan, Ahmed Gomaa; Salama, Khaled N. ( 0000-0001-7742-1282 )
Abstract:
This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations. © 2013 ETRI.
KAUST Department:
Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Sensors Lab
Publisher:
Electronics and Telecommunications Research Institute (ETRI)
Journal:
ETRI Journal
Issue Date:
1-Jun-2013
DOI:
10.4218/etrij.13.0112.0677
Type:
Article
ISSN:
12256463
Appears in Collections:
Articles; Electrical Engineering Program; Sensors Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorBarakat, Mohamed L.en
dc.contributor.authorMansingka, Abhinav S.en
dc.contributor.authorRadwan, Ahmed Gomaaen
dc.contributor.authorSalama, Khaled N.en
dc.date.accessioned2015-08-03T11:06:10Zen
dc.date.available2015-08-03T11:06:10Zen
dc.date.issued2013-06-01en
dc.identifier.issn12256463en
dc.identifier.doi10.4218/etrij.13.0112.0677en
dc.identifier.urihttp://hdl.handle.net/10754/562799en
dc.description.abstractThis paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations. © 2013 ETRI.en
dc.publisherElectronics and Telecommunications Research Institute (ETRI)en
dc.subjectChaosen
dc.subjectFPGAen
dc.subjectPost-processingen
dc.subjectPseudorandom number generatoren
dc.titleGeneralized hardware post-processing technique for chaos-based pseudorandom number generatorsen
dc.typeArticleen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentSensors Laben
dc.identifier.journalETRI Journalen
dc.contributor.institutionDepartment of Engineering Mathematics, Cairo University, Giza, Egypten
dc.contributor.institutionNanoelectronics Integrated Systems Center (NISC), Nile University, Egypten
kaust.authorBarakat, Mohamed L.en
kaust.authorMansingka, Abhinav S.en
kaust.authorSalama, Khaled N.en
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