High-performance silicon nanotube tunneling FET for ultralow-power logic applications

Handle URI:
http://hdl.handle.net/10754/562674
Title:
High-performance silicon nanotube tunneling FET for ultralow-power logic applications
Authors:
Fahad, Hossain M.; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 )
Abstract:
To increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.
KAUST Department:
Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Publisher:
Institute of Electrical and Electronics Engineers
Journal:
IEEE Transactions on Electron Devices
Issue Date:
Mar-2013
DOI:
10.1109/TED.2013.2243151
Type:
Article
ISSN:
00189383
Sponsors:
This work was supported by the Office of Sponsored Research at King Abdullah University of Science and Technology under Competitive Research Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor W. Tsai.
Appears in Collections:
Articles; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorFahad, Hossain M.en
dc.contributor.authorHussain, Muhammad Mustafaen
dc.date.accessioned2015-08-03T11:00:54Zen
dc.date.available2015-08-03T11:00:54Zen
dc.date.issued2013-03en
dc.identifier.issn00189383en
dc.identifier.doi10.1109/TED.2013.2243151en
dc.identifier.urihttp://hdl.handle.net/10754/562674en
dc.description.abstractTo increase typically low output drive currents from tunnel field-effect transistors (FETs), we show a silicon vertical nanotube (NT) architecture-based FET's effectiveness. Using core (inner) and shell (outer) gate stacks, the silicon NT tunneling FET shows a sub-60 mV/dec subthreshold slope, ultralow off -state leakage current, higher drive current compared with gate-all-around nanowire silicon tunnel FETs. © 1963-2012 IEEE.en
dc.description.sponsorshipThis work was supported by the Office of Sponsored Research at King Abdullah University of Science and Technology under Competitive Research Grant CRG-1-2012-HUS-008. The review of this paper was arranged by Editor W. Tsai.en
dc.publisherInstitute of Electrical and Electronics Engineersen
dc.subjectBTBTen
dc.subjecthigh performanceen
dc.subjectnanotube (NT)en
dc.subjectsiliconen
dc.titleHigh-performance silicon nanotube tunneling FET for ultralow-power logic applicationsen
dc.typeArticleen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.identifier.journalIEEE Transactions on Electron Devicesen
kaust.authorFahad, Hossain M.en
kaust.authorHussain, Muhammad Mustafaen
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