Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays

Handle URI:
http://hdl.handle.net/10754/562423
Title:
Fabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arrays
Authors:
Zhai, Yujia; Palard, Marylene; Mathew, Leo; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 ) ; Willson, Grant Grant; Tutuc, Emanuel; Banerjee, Sanjay Kumar
Abstract:
We report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpuf
KAUST Department:
Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Publisher:
Bentham Science Publishers Ltd.
Journal:
Micro and Nanosystems
Issue Date:
26-Nov-2012
DOI:
10.2174/1876402911204040333
Type:
Article
ISSN:
18764029
Appears in Collections:
Articles; Electrical Engineering Program; Integrated Nanotechnology Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorZhai, Yujiaen
dc.contributor.authorPalard, Maryleneen
dc.contributor.authorMathew, Leoen
dc.contributor.authorHussain, Muhammad Mustafaen
dc.contributor.authorWillson, Grant Granten
dc.contributor.authorTutuc, Emanuelen
dc.contributor.authorBanerjee, Sanjay Kumaren
dc.date.accessioned2015-08-03T10:37:41Zen
dc.date.available2015-08-03T10:37:41Zen
dc.date.issued2012-11-26en
dc.identifier.issn18764029en
dc.identifier.doi10.2174/1876402911204040333en
dc.identifier.urihttp://hdl.handle.net/10754/562423en
dc.description.abstractWe report fabrication of single crystalline silicon nanowire based-three-dimensional MIS nano-capacitors for potential analog and mixed signal applications. The array of nanowires is patterned by Step and Flash Imprint Lithography (S-FIL). Deep silicon etching (DSE) is used to form the nanowires with high aspect ratio, increase the electrode area and thus significantly enhance the capacitance. High-! dielectric is deposited by highly conformal atomic layer deposition (ALD) Al2O3 over the Si nanowires, and sputtered metal TaN serves as the electrode. Electrical measurements of fabricated capacitors show the expected increase of capacitance with greater nanowire height and decreasing dielectric thickness, consistent with calculations. Leakage current and time-dependent dielectric breakdown (TDDB) are also measured and compared with planar MIS capacitors. In view of greater interest in 3D transistor architectures, such as FinFETs, 3D high density MIS capacitors offer an attractive device technology for analog and mixed signal applications. - See more at: http://www.eurekaselect.com/105099/article#sthash.EzeJxk6j.dpufen
dc.publisherBentham Science Publishers Ltd.en
dc.titleFabrication of three-dimensional MIS nano-capacitor based on nano-imprinted single crystal silicon nanowire arraysen
dc.typeArticleen
dc.contributor.departmentElectrical Engineering Programen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.identifier.journalMicro and Nanosystemsen
dc.contributor.institutionMicroelectronics Research Center, The University of Texas at Austin, Austin, TX 78758, United Statesen
dc.contributor.institutionAstroWatt, Inc, 10100 Burnet Rd, Bldg. 160, Austin, TX 78758, United Statesen
kaust.authorHussain, Muhammad Mustafaen
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