Huffman-based code compression techniques for embedded processors

Handle URI:
http://hdl.handle.net/10754/561550
Title:
Huffman-based code compression techniques for embedded processors
Authors:
Bonny, Mohamed Talal; Henkel, Jörg
Abstract:
The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.
KAUST Department:
Physical Sciences and Engineering (PSE) Division
Publisher:
Association for Computing Machinery (ACM)
Journal:
ACM Transactions on Design Automation of Electronic Systems
Issue Date:
1-Sep-2010
DOI:
10.1145/1835420.1835424
Type:
Article
ISSN:
10844309
Appears in Collections:
Articles; Physical Sciences and Engineering (PSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorBonny, Mohamed Talalen
dc.contributor.authorHenkel, Jörgen
dc.date.accessioned2015-08-02T09:14:00Zen
dc.date.available2015-08-02T09:14:00Zen
dc.date.issued2010-09-01en
dc.identifier.issn10844309en
dc.identifier.doi10.1145/1835420.1835424en
dc.identifier.urihttp://hdl.handle.net/10754/561550en
dc.description.abstractThe size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.en
dc.publisherAssociation for Computing Machinery (ACM)en
dc.subjectCode compressionen
dc.subjectCode densityen
dc.subjectEmbedded systemsen
dc.subjectHuffman codingen
dc.titleHuffman-based code compression techniques for embedded processorsen
dc.typeArticleen
dc.contributor.departmentPhysical Sciences and Engineering (PSE) Divisionen
dc.identifier.journalACM Transactions on Design Automation of Electronic Systemsen
dc.contributor.institutionUniversity of Karlsruhe, Germanyen
kaust.authorBonny, Mohamed Talalen
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