Si/Ge hetero-structure nanotube tunnel field effect transistor

Handle URI:
http://hdl.handle.net/10754/346750
Title:
Si/Ge hetero-structure nanotube tunnel field effect transistor
Authors:
Hanna, A. N.; Hussain, Muhammad Mustafa ( 0000-0003-3279-0441 )
Abstract:
We discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.
KAUST Department:
Integrated Nanotechnology Lab
Citation:
Si/Ge hetero-structure nanotube tunnel field effect transistor 2015, 117 (1):014310 Journal of Applied Physics
Publisher:
AIP Publishing
Journal:
Journal of Applied Physics
Issue Date:
7-Jan-2015
DOI:
10.1063/1.4905423
Type:
Article
ISSN:
0021-8979; 1089-7550
Additional Links:
http://scitation.aip.org/content/aip/journal/jap/117/1/10.1063/1.4905423
Appears in Collections:
Articles; Integrated Nanotechnology Lab

Full metadata record

DC FieldValue Language
dc.contributor.authorHanna, A. N.en
dc.contributor.authorHussain, Muhammad Mustafaen
dc.date.accessioned2015-03-17T06:08:31Zen
dc.date.available2015-03-17T06:08:31Zen
dc.date.issued2015-01-07en
dc.identifier.citationSi/Ge hetero-structure nanotube tunnel field effect transistor 2015, 117 (1):014310 Journal of Applied Physicsen
dc.identifier.issn0021-8979en
dc.identifier.issn1089-7550en
dc.identifier.doi10.1063/1.4905423en
dc.identifier.urihttp://hdl.handle.net/10754/346750en
dc.description.abstractWe discuss the physics of conventional channel material (silicon/germanium hetero-structure) based transistor topology mainly core/shell (inner/outer) gated nanotube vs. gate-all-around nanowire architecture for tunnel field effect transistor application. We show that nanotube topology can result in higher performance through higher normalized current when compared to nanowire architecture at Vdd-=-1-V due to the availability of larger tunneling cross section and lower Shockley-Reed-Hall recombination. Both architectures are able to achieve sub 60-mV/dec performance for more than five orders of magnitude of drain current. This enables the nanotube configuration achieving performance same as the nanowire architecture even when Vdd is scaled down to 0.5-V.en
dc.publisherAIP Publishingen
dc.relation.urlhttp://scitation.aip.org/content/aip/journal/jap/117/1/10.1063/1.4905423en
dc.rightsArchived with thanks to Journal of Applied Physicsen
dc.titleSi/Ge hetero-structure nanotube tunnel field effect transistoren
dc.typeArticleen
dc.contributor.departmentIntegrated Nanotechnology Laben
dc.identifier.journalJournal of Applied Physicsen
dc.eprint.versionPublisher's Version/PDFen
dc.contributor.affiliationKing Abdullah University of Science and Technology (KAUST)en
kaust.authorHanna, Amiren
kaust.authorHussain, Muhammad Mustafaen
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