Hardware Realization of Chaos-based Symmetric Video Encryption

Handle URI:
http://hdl.handle.net/10754/293352
Title:
Hardware Realization of Chaos-based Symmetric Video Encryption
Authors:
Ibrahim, Mohamad A.
Abstract:
This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.
Advisors:
Keyes, David E. ( 0000-0002-4052-7224 )
Committee Member:
Al-Naffouri, Tareq Y.; Alouini, Mohamed-Slim ( 0000-0003-4827-1793 ) ; Salama, Khaled N. ( 0000-0001-7742-1282 )
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Program:
Computer Science
Issue Date:
May-2013
Type:
Thesis
Appears in Collections:
Theses; Computer Science Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.advisorKeyes, David E.en
dc.contributor.authorIbrahim, Mohamad A.en
dc.date.accessioned2013-06-03T18:37:33Z-
dc.date.available2013-06-03T18:37:33Z-
dc.date.issued2013-05en
dc.identifier.urihttp://hdl.handle.net/10754/293352en
dc.description.abstractThis thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.en
dc.language.isoenen
dc.subjectMPEG2en
dc.subjectEncryptionen
dc.subjectVideoen
dc.subjectSecurityen
dc.subjecthardwareen
dc.titleHardware Realization of Chaos-based Symmetric Video Encryptionen
dc.typeThesisen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
thesis.degree.grantorKing Abdullah University of Science and Technologyen_GB
dc.contributor.committeememberAl-Naffouri, Tareq Y.en
dc.contributor.committeememberAlouini, Mohamed-Slimen
dc.contributor.committeememberSalama, Khaled N.en
thesis.degree.disciplineComputer Scienceen
thesis.degree.nameMaster of Scienceen
dc.person.id118380en
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