Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator

Handle URI:
http://hdl.handle.net/10754/236251
Title:
Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator
Authors:
Mansingka, Abhinav S.; Radwan, Ahmed G.; Salama, Khaled N. ( 0000-0001-7742-1282 ) ; Zidan, Mohammed A. ( 0000-0003-3843-814X )
Abstract:
This paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division; Sensors Lab
Citation:
Mansingka AS, Radwan AG, Zidan MA, Salama KN (2011) Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/MWSCAS.2011.6026596.
Publisher:
Institute of Electrical and Electronics Engineers (IEEE)
Journal:
2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)
Conference/Event name:
54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Issue Date:
29-Jul-2012
DOI:
10.1109/MWSCAS.2011.6026596
Type:
Conference Paper
Additional Links:
http://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6026596
Appears in Collections:
Conference Papers; Sensors Lab; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.authorMansingka, Abhinav S.en
dc.contributor.authorRadwan, Ahmed G.en
dc.contributor.authorSalama, Khaled N.en
dc.contributor.authorZidan, Mohammed A.en
dc.date.accessioned2012-07-29T21:02:50Z-
dc.date.available2012-07-29T21:02:50Z-
dc.date.issued2012-07-29en
dc.identifier.citationMansingka AS, Radwan AG, Zidan MA, Salama KN (2011) Analysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillator. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). doi:10.1109/MWSCAS.2011.6026596.en
dc.identifier.doi10.1109/MWSCAS.2011.6026596en
dc.identifier.urihttp://hdl.handle.net/10754/236251en
dc.description.abstractThis paper introduces the first fully digital implementation of a 3rd order ODE-based chaotic oscillator with signum nonlinearity. A threshold bus width of 12-bits for reliable chaotic behavior is observed, below which the system output becomes periodic. Beyond this threshold, the maximum Lyapunov exponent (MLE) is shown to improve up to a peak value at 16-bits and subsequently decrease with increasing bus width. The MLE is also shown to gradually increase with number of introduced internal delay cycles until a peak value at 14 cycles, after which the system loses chaotic properties. Introduced external delay cycles are shown to rotate the attractors in 3-D phase space. Bus width and delay elements can be independently modulated to optimize the system to suit specifications. The experimental results of the system show low area and high performance on a Xilinx Virtex 4 FPGA with throughput of 13.35 Gbits/s for a 32-bit implementation.en
dc.language.isoenen
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)en
dc.relation.urlhttp://ieeexplore.ieee.org/lpdocs/epic03/wrapper.htm?arnumber=6026596en
dc.titleAnalysis of bus width and delay on a fully digital signum nonlinearity chaotic oscillatoren
dc.typeConference Paperen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
dc.contributor.departmentSensors Laben
dc.identifier.journal2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)en
dc.conference.date7 August 2011 through 10 August 2011en
dc.conference.name54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011en
dc.conference.locationSeoulen
kaust.authorMansingka, Abhinav S.en
kaust.authorRadwan, Ahmed G.en
kaust.authorZidan, Mohammed A.en
kaust.authorSalama, Khaled N.en
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