Hardware Realization of Chaos Based Symmetric Image Encryption

Handle URI:
http://hdl.handle.net/10754/234953
Title:
Hardware Realization of Chaos Based Symmetric Image Encryption
Authors:
Barakat, Mohamed L.
Abstract:
This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.
Advisors:
Salama, Khaled Nabil
Committee Member:
Al-Naffouri, Tareq Y.; Alouini, Mohamed-Slim ( 0000-0003-4827-1793 )
KAUST Department:
Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division
Program:
Electrical Engineering
Issue Date:
Jun-2012
Type:
Thesis
Appears in Collections:
Theses; Electrical Engineering Program; Computer, Electrical and Mathematical Sciences and Engineering (CEMSE) Division

Full metadata record

DC FieldValue Language
dc.contributor.advisorSalama, Khaled Nabilen
dc.contributor.authorBarakat, Mohamed L.en
dc.date.accessioned2012-07-21T08:22:42Z-
dc.date.available2012-07-21T08:22:42Z-
dc.date.issued2012-06en
dc.identifier.urihttp://hdl.handle.net/10754/234953en
dc.description.abstractThis thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.en
dc.language.isoenen
dc.subjectChaosen
dc.subjectFPGAen
dc.subjectNISTen
dc.subjectPost-Processingen
dc.subjectBlack and stream ciphersen
dc.subjectImage encryptionen
dc.titleHardware Realization of Chaos Based Symmetric Image Encryptionen
dc.typeThesisen
dc.contributor.departmentComputer, Electrical and Mathematical Sciences and Engineering (CEMSE) Divisionen
thesis.degree.grantorKing Abdullah University of Science and Technologyen_GB
dc.contributor.committeememberAl-Naffouri, Tareq Y.en
dc.contributor.committeememberAlouini, Mohamed-Slimen
thesis.degree.disciplineElectrical Engineeringen
thesis.degree.nameMaster of Scienceen
dc.person.id113030en
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